1. Field of the Invention
This invention relates to microlithography in the manufacture of integrated circuit chips on wafers and to the measurement of overlay of the first layer.
2. Description of Related Art
In microlithography, difficulties exist in the accurate measurement of overlay (O/L), which comprises the degree of misalignment between successive layers of patterns on a thin film electronic structure and in aligning the masks/reticles used to print such layers to preceding layers.
In microlithography, the measurement of overlay is important. Overlay, as used here, comprises the degree of misalignment between successive layers of patterns on thin film electronic structures and the preceding layers.
Some commercially available exposure systems use a method to align the wafers. When using the global alignment method, global alignment marks are patterned by an independent process layer (so called zeroth layer), then all the device process layers are aligned to the global alignment marks. For all of the device layers beside the first layer, there are some existing technologies to measure the degree of overlay shift. All of these measurement technologies use some specially designed representative patterns, which come from both successive and preceding layers, on scribe lines to check the overlay. For the first layer, which can be made by a process such as the formation of a well in a CMOS (Complementary Metal Oxide Semiconductor) device, it is difficult to determine the overlay because there are no preceding inspection patterns of the (zeroth) layer on the scribe lines. That makes for considerable rework and/or scrap when the exposure system has an overlay shift problem. At the same time, much time is required to check the machine and the production must be interrupted when one doubts that the overlay performance of one exposure system is satisfactory.
FIGS. 1A, 1B, 2A and 2B show an example of a prior art system for overlay measurement of device layers.
FIG. 1A shows a plan view of a substrate 10 with a first, large, mother box M patterned as an overlay inspection (mother) feature. Mother box M is patterned in the first layer 12 formed on substrate 10.
FIG. 1B is an elevation view of FIG. 1A with showing mother box M comprising a shaped pattern formed in the layer 12 which overlies the substrate 10.
FIG. 2A shows the product of FIGS. 1A and 1B after forming a second, smaller, child box C in a successive second layer 14 which overlies the first layer 12. The smaller child box C is patterned from the large mother box M (the mother feature) in the preceding layer 12. The small box C formed in the second layer 14 formed by this process comprises the child overlay inspection feature.
Referring to FIG. 2B, X1 represents the distance between the left edges of the mother box M and the child box C. The distance X2 is the distance between the right edges of the mother box M and the child box C. The centers of these two boxes M and C are designed at the same position so the overlay of the successive layer to the preceding layer can be determined by the formula as follows: EQU Overlay shift=(X2-X1)/2.
FIGS. 3A-3D and FIGS. 4A-4B show an example of a prior art wafer being processed by the prior art global alignment method.
FIG. 3A shows a bright new wafer 20 which is shown to be without any pattern thereon.
FIG. 3B is the wafer 20 after zeroth layer process, with global alignment marks 22 and 22' which have been patterned on wafer 20 for the alignment of following layers.
FIG. 3C shows the wafer 20 after the patterning process of the first layer 21 formed on wafer 20 by use of a prior art process of manufacture of chip forming representative patterns 23' and 23" in an array of patterns formed from the first layer 21.
To the right of FIG. 3C, FIG. 4A shows a blown up image 24 showing a pattern 23 which is a magnified image representing patterns 23' and 23". The box pattern 23 is formed in the first layer 21. The pattern 23 is patterned at scribe lines as the mother overlay inspection feature for measurement of overlay in successive layers.
FIG. 3D shows the wafer 20 after the process of patterning another layer subsequent to the first layer 21 forming a child overlay inspection features on the mother overlay features 23', 23" as is illustrated in FIG. 4B.
FIG. 4B is a blown up area 24 on the wafer 20 shown in FIG. 3D showing magnified images illustrative of the overlay inspection features 23 and 26. The smaller box 26 is patterned in the upper layer in the same position as the mother box 23 providing a mother/child overlay inspection set of features.
Similarly to the markings seen in FIGS. 1A, 1B, 2A and 2B, the combination of mother box 23 and child box 26 can be used to the measure overlay of any layers beside the first layer. This illustrates the problem of conventional technology. The layers formed after the first layer 21 have one or more preceding layer(s) to measure the overlay but there is no layer preceding to the first layer to print the mother overlay inspection feature (big box 23, for example) in scribe lines.
Therefore it is difficult to determine the overlay of the first layer such as layer 12 in FIG. 2B and layer 23 in FIG. 3D, in a conventional process.